With the tremendous advances in process technology and the non-scalability of complex monolithic designs, multicore architecture is becoming the design of choice for high-end machines to embedded devices. The number of cores per chip is expected to grow, even to double, every two years. Although these advances are providing us with a lot of opportunities, they are also giving us a lot of design challenges, such as bandwidth requirement, power (both static and dynamic), memory wall, parallelization, etc…

This forum aims to provide an avenue to foster communication among academia and industry in all aspects of next-generation multicore technologies, such as the Cell BE processor. Authors are invited to submit high quality papers representing their original work in (but not limited to) the following topics targeting multicore/manycore processors:

• Parallel programming models

• Specific applications

• Performance modeling and analysis (including software caching and prefetching)

• Thread management and thread-level speculation (including scheduling and load-balancing)

• Cache hierarchy design

• Interconnection and network on chip

• Power-aware design

• Simulation tools

• Compilation techniques

• Homogeneous and heterogeneous architecture

• Security issues